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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . l i + c h a r g e r p r o t e c t i o n i c provide out pin 5v voltage clamping protection thermal charging regulation protection provide input over-voltage protection provide input over-current protection provide over temperature protection provide reverse current blocking high immunity of false triggering high accuracy protection threshold low on resistance 0.3 w typ. compact tdfn2x2-8 and dfn3x3-8 packages lead free and green devices available (rohs compliant) f e a t u r e s a p p l i c a t i o n s cell phones g e n e r a l d e s c r i p t i o n s i m p l i f i e d a p p l i c a t i o n c i r c u i t the APL3225 provides complete li+ charger protection against input over-voltage, input over-current and over- temperature. when any of the monitored parameters is over the threshold, the ic turns off the charging current. all protections also have deglitch time against false trig- gering due to voltage spikes or current transients. the APL3225 integrates a 5.5v ldo to prevent acin over- shoot reaching chr_ldo and out. when any transient peak voltage above 5.5v presenting in acin pin, but be- low ovp threshold, the internal ldo will clamp its output at 5.5v. when acin voltage exceeds ovp threshold, the device will turn off charging current. the charging current is controlled by the gatdrv pin. when sourcing a cur- rent from the gatdrv pin, the out pin delivers the charg- ing current which is 200-fold magnified in amplitude based on gatdrv?s current. other features include accurate v vcdt /v acin voltage divider, reverse current blocking from out to acin and otp protection. the APL3225 provides complete li+ charger protections, and saves the external mosfet and schottky diode for the charger of cell phone?s pmic. the above features and small package make the APL3225 an ideal part for cell phones applications. p i n c o n f i g u r a t i o n acin 1 acin 2 vcdt 4 5 gatdrv gnd 3 8 out 7 out 6 chr _ ldo tdfn 2 x 2 - 8 ( top view ) = exposed pad ( connected to ground plane for better heat dissipation ) dfn 3 x 3 - 8 ( top view ) acin 1 gnd 3 8 out acin 2 vcdt 4 7 out 5 gatdrv 6 chr _ ldo acin gnd apl 3225 pmic chr _ ldo vcdt gatdrv out 5 v adapter vcdt gatdrv chr _ ldo isens vbat li + battery
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n a b s o l u t e m a x i m u m r a t i n g s (note 1) symbol parameter rating unit v acin aci n input voltage ( acin to gnd) - 0.3 ~ 28 v v chr_ldo chr_ldo to gnd voltage - 0.3 ~ 7 v v gatdrv gatdrv to gnd voltage - 0.3 ~ v chr_ldo v v cdt vcdt to gnd voltage - 0.3 ~ 7 v v out out to gnd voltage - 0.3 ~ 7 v i out out put current (out to gnd) 2 a t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature ( 10 seconds ) 26 0 o c symbol parameter typical value unit q ja tdfn2x2 - 8 junction - to - ambient resistance in free air (note 2) 75 o c/w q ja dfn3x3 - 8 junction - to - ambient resistance in free air (note 2) 65 o c/w t h e r m a l c h a r a c t e r i s t i c note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tdfn2x2-8 is soldered directly on the pcb. n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . note 1:stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ?recom- mended operating conditions?is not implied. exposure to absolute maximum rating conditions for extended periods may affect vice reliability. apl 3225 package code operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material handling code temperature range package code x - date code g : halogen and lead free device assembly material qb : tdfn 2 x 2 - 8 apl 32 25 qb : l 25 x q a : dfn 3 x 3 - 8 x - date code apl 32 25 q a : apl 3225 xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 3 symbol parameter range unit v acin acin input voltage 4.5 ~ 6.5 v i out output current 0 ~ 1 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c c chr_ldo chr_ldo output capacitor 1 m f r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s (note 3) note 3: refer to the typical application circuit unless otherwise specified, these specifications apply over v acin =5v, t a = -40 ~ 85 o c. typical values are at t a =25 o c. e l e c t r i c a l c h a r a c t e r i s t i c s APL3225 symbol parameter test conditions min . typ . max . unit acin input current and power - on - reset (por) i out =0a, i chr_ldo =0a - 350 600 m a in otp - - 550 m a i acin acin supply current v acin >v ovp - - 550 m a v por acin por threshold v acin rising 2.4 2.6 2.8 v acin por hysteresis - 250 - mv t b(acin) acin power - on blanking time - 8 - ms internal switch on resistance acin to out on resistance i out = 1 a - 0.3 0.35 w chr_ldo discharge resistnace v acin = 12v , v chr_ldo = 2v - 500 - w input over - voltage protection (ovp) v reg internal ldo output voltage v acin = 6 v, i out = 10ma, t j = - 40 ~ 125 o c 5.265 5.5 5.735 v ldo output series resistance 2.4 3 3.6 k w v ovp in put ovp threshold APL3225 v acin rising, t j = - 40 ~ 125 o c 6.6 6.8 7 v input ovp hysteresis 150 200 250 mv t ovp input ovp propagation delay - - 1 m s t on(ovp) input ovp recovery time - 1 - ms over - current protection (ocp) i oc over - current trip thres hold t j = 25 o c , t j = - 40 ~ 25 o c 1.5 - - a i cl current limit level t j = 25 o c , t j = - 40 ~ 25 o c 1.2 - - a vcdt internal divider divider ratio v vcdt /v acin 0.1035 0.1056 0.1078 v/v charge current control current mirror gain i out = 0.6a, i out /i gatdrv 100 200 300 a/a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 4 unless otherwise specified, these specifications apply over v acin =5v, t a = -40 ~ 85 o c. typical values are at t a =25 o c. e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APL3225 symbol parameter test conditions min . typ . max . unit r everse c urrent b locking pmos lockout threshold - 20 - mv pmos lockout release threshold - 150 - mv out input current (reverse current blocking) v acin = 0v, v out = 4.2v, v gatdrv =0v - - 1 m a vout overshoot clamp v ccamp overshoot clamp rising threshold v out rising slew rate > 0.2v/ m s 4.6 4.8 5.0 v overshoot clamp pull low resistance v out rising slew rate > 0.2v/ m s - 3 - w overshoot clamp active time from overshoot clamp threshold being surpassed - 150 - m s thermal shutdown protection t otp thermal shutdown threshold t j rising - 160 - c thermal shutdown hysteresis - 40 - c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 5 p i n d e s c r i p t i o n pin no name function 1 2 acin power supply input. connect this pin to external dc supply. bypass to gnd with a 1 m f (minimum) ceramic capacitor. 3 gnd ground terminal. 4 vcdt provide an interval voltage divider. this pin divides acin voltage into 39 /369 ratio. 5 gatdrv charging current control pin. when sourcing a current from this pin, the out pin will source out a current whose magnitude is 200 x i gatdrv . 6 chr_ldo output pin. the pin provides supply voltage to the pmic input. bypass to gnd with a 1 m f (minimum) ceramic capacitor. 7 output pins. the pin provides supply source current in series with a resistor to battery. 8 out this pin possesses the overshoot clamp function to limit peak voltage. exposed pad - exposed thermal pad. must be electric ally connected to the gnd pin.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 6 b l o c k d i a g r a m t y p i c a l a p p l i c a t i o n c i r c u i t gatdrv chr _ ldo vcdt out gnd acin overshoot clamp acin gnd apl 3225 pmic 0 . 2 w 1 m f 1 m f chr _ ldo vcdt gatdrv out 5 v adapter vcdt gatdrv chr _ ldo isens vbat li + battery c 1 c 2 1 , 2 3 4 7 , 8 6 5 designation description 1 m f, 25v, x5r, 0603 murata grm 188r61e105k c acin 1 m f, 16v, x5r, 0603 murata grm 188r61c105k c chr_ldo 1 m f, 6.3v, x5r, 0603 murata grm 185r60j225ke26
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 7 f u n c t i o n d e s c r i p t i o n acin power-on-reset (por) the APL3225 is built-in a power-on-reset circuit to keep the output shut off until internal circuitry is operating properly. the por circuit has hysteresis and a de-glitch feature so that it will typically ignore undershoot transients on the input. when input voltage exceeds the por thresh- old and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. acin over-voltage protection (ovp) and ldo mode operation the chr_ldo output of the ic operates similar to a lin- ear regulator. when the acin input voltage is less than v reg , and above the acin por v acin , the internal ldo output voltage tracks the input voltage with a voltage drop caused by r ds(on) of mosfet q1. when the acin input voltage is greater than v reg plus the r ds(on) drop of q1, and less than v ovp , the internal ldo output voltage is regulated to v reg , and this is also referred as ldo mode operation. if the input voltage rises above v ovp , the inter- nal fet q1 and q2 will be turned off within 1 m s to protect connected system on out pin. when the input voltage returns below the input ovp threshold minus the hysteresis, the fets is turned on again after 1ms recov- ery time. the input ovp circuit has a 200mv hysteresis and a recovery time of t on(ovp) to provide noise immunity against transient conditions. charging current control the charging current is controlled by the gatdrv pin. when sourcing a current from the gatdrv pin, the out pin delivers the charging current which is 200-fold mag- nified in amplitude based on gatdrv?s current. the i out current can be calculated by this following equation: i out =200xi gatdrv where the i out is the current flowing out from out pin. the i gatdrv is the current flowing out from gatdrv pin. current limit the output current is monitored by the internal current limit circuit. when the output current reaches the current limit threshold, the device limits the output current at cur- rent limit threshold. the current limit level decrease as the junction temperature increase. when the junction temperature increases, the internal current limit circuit reduces the current limit level, allowing the device?s junc- tion temperature to cool down. internal p-mosfet and reverse current blocking the APL3225 integrates a p-channel mosfet with the body diode reverse protection to replace the external pnp transistor and schottky diode for cell phone?s pmic. the body diode reverse protection prevents battery voltage supplies to chr_ldo and acin pin. when the p-chan- nel mosfet?s negative v sd voltage is detected, the inter- nal bulk selection circuitry will switch the body diode of the p-channel mosfet forward biased from source to drain, meanwhile the p-channel is turned off regardless of gatdrv?s current. this after the detection of negative v sd , the p-channel mosfet is in lockout state to prevent battery discharging from acin and chr_ldo to external circuitry. the p-channel mosfet lockout will be releases when positive v sd is detected. t h i s o u t p i n p o s s e s s e s t h e o v e r s h o o t c l a m p f u n c t i o n t o l i m i t p e a k v o l t a g e . s i n c e t h e c l a m p i n g f u n c t i o n n e e d s a l o w r e s i s t a n c e p a t h b e t w e e n o u t p i n a n d e x t e r n a l h i g h v o l t a g e s o u r c e ( i n a b n o r m a l c o n d i t i o n ) , p l e a s e c o n n e c t t h i s o u t p i n d i r e c t l y t o o u t s i d e c i r c u i t t o l e t c l a m p i n g w o r k . o u t o v e r s h o o t c l a m p
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 8 a p p l i c a t i o n i n f o r m a t i o n capacitor selection the input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. in the ac adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. a 25v, x5r, dielectric ceramic capacitor with a value be- tween 1 m f and 4.7 m f placed close to the acin pin is recommended. the output capacitor of chr_ldo is for chr_ldo volt- age decoupling. and also can be as the input capacitor of the charging circuit. at least, a 1 m f, 10v, x5r capacitor is recommended. layout consideration in some failure modes, a high voltage may be applied to the device. make sure the clearance constraint of the pcb layout must satisfy the design rule for high voltage. the exposed pad of the tdfn2x2-8 and dfn3x3-8 performs the function of channeling heat away. it is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through sev- eral thermal vias to improve heat dissipation. the input and output capacitors should be placed close to the ic. the high current traces like input trace and output trace must be wide and short. recommended minimum footprint tdfn 2 x 2 - 8 thermal via diameter 12 mil x 5 ground plane for thermal pad 0 . 241 mm 0 . 508 mm 0 . 222 mm 0 . 8 mm 0 . 572 mm 1 . 2 9 5 m m thermal via diameter 12 mil x 5 ground plane for thermal pad 0 . 305 mm 0 . 66 mm 0 . 305 mm 0 . 61 mm dfn 3 x 3 - 8 1 . 575 mm 2 . 1 4 6 m m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 9 p a c k a g e i n f o r m a t i o n t d f n 2 x 2 - 8 min. max. 0.80 0.00 0.18 0.30 1.00 1.60 0.05 0.60 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn2x2-8 0.30 0.45 1.00 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.039 0.063 0.024 0.012 0.018 0.70 0.039 0.028 0.002 0.50 bsc 0.020 bsc s y m b o l 1.90 2.10 0.075 0.083 1.90 2.10 0.075 0.083 d e a b a1 a3 d2 e 2 l e pin 1 corner note : 1. follow from jedec mo-229 wccd-3.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 0 p a c k a g e i n f o r m a t i o n dfn3x3-8 s y m b o l min. max. 1.00 0.00 0.25 0.35 1.90 2.40 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref dfn3x3-8 0.30 0.50 1.75 0.008 ref min. max. inches 0.039 0.000 0.010 0.014 0.075 0.094 0.055 0.012 0.020 0.80 0.069 0.031 0.002 0.65 bsc 0.026 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 d e pin 1 a a1 a3 b d2 pin 1 corner e e 2 k l
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 1 d e v i c e s p e r u n i t package type unit quantity tdfn2x2 - 8 tape & reel 3000 dfn3x3 - 8 tape & reel 3000 c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.50 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn2x2 - 8 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.4 2.35 min 2.35 mi n 1.00 ? 0.20 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 dfn3x3 - 8 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0. 6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 2 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 2 x 2 - 8 user direction of feed dfn3x3-8 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 3 c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 4 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - n o v . , 2 0 1 2 a p l 3 2 2 5 w w w . a n p e c . c o m . t w 1 5 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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